1. Field of the Invention
The present invention generally relates to cache-memory-control systems, and particularly relates to a cache-memory-control system which achieves an enhanced system performance by introducing cache arbitration.
2. Description of the Related Art
FIG. 1 is a schematic diagram of a related-art system.
A configuration of FIG. 1 includes a central-control unit 10, a cache memory 11 provided in the central-control unit 10, a main memory 2, an input/output-control device 3, and a system bus 4 which connects between these elements. The cache memory 11 stores instructions and data of frequent use and initially stored in the main memory 2 with aim of eliminating a need for the central-control unit 10 to access the main memory 2 each time such instructions and data become necessary. Namely, the cache memory 11 is a temporal storage capable of a high-speed operation.
In the system as described above, a cache-control unit monitors an address used when the input/output-control device 3 accesses the main memory 2. In general, such a system is provided with a bus-snoop function in order to avoid data inconsistency between the cache memory 11 and the main memory 2. Such data inconsistency may arise when data is written in the main memory 2 by use of a DMA (direct memory access) mode.
A measure generally taken to achieve the bus-snoop function includes invalidating cache data when the DMA-write access is directed to an address encompassed by the cache memory 11. In such a scheme, the bus-snoop function monitors the system bus 4 during a period when the input/output-control device 3 accesses the main memory 2 by use of a DMA mode. During this period, the central-control unit 10 cannot gain access to the cache memory 11, and has to wait until the access is granted.
There are some systems which are provided with a cache memory for instructions and a separate cache memory for operands. In such systems, an operand-write operation, which is initiated upon execution of an instruction by central-control unit, is only reflected by the operand cache. When there is a need to rewrite instructions, on the other hand, the instruction cache is invalidated in an entirety thereof in order to avoid data inconsistency with the main memory. Alternatively, an instruction-cache invalidating mode may be provided to take effect during a write operation, and invalidates a particular set of data in the instruction cache when the write address matches.
In order to overcome problems associated with the first scheme described above, Japanese Laid-open Patent Applications No. 5-97378 and No. 6-94821 disclose a bus-snoop control unit which is provided with a buffer as a temporal storage of DMA addresses. In this scheme, the cache invalidating operation is performed when a CPU becomes available, thereby avoiding a reduction in a processor-bus performance. If the buffer becomes full, however, the DMA operation has to be stopped, or the cache memory in its entirety has to be invalidated. This results in affecting the system performance.
In the case of the systems having both an instruction cache and an operand cache, generally, whole contents of the instruction cache are invalidated in order to avoid data inconsistency between the cache and the main memory. Nullification of all the cache contents inevitably brings down the system performance. In the case in which a only particular set of data in the instruction cache is invalidated when write addresses match during the instruction-cache invalidating mode, there is another problem in that operations for loading instructions are aborted each time the write access is made.
Accordingly, there is a need for a cache-memory-control system which can enhance system performance.
Accordingly, it is a general object of the present invention to provide a cache-memory-control system which can satisfy the need described above.
It is another and more specific object of the present invention to provide a cache-memory-control system which can enhance system performance.
In order to achieve above object according to the present invention, a system includes a main-memory unit, an input/output-control unit which performs a write operation with respect to the main-memory unit by way of direct memory access, and a central-control unit which operates based on information stored in the main-memory unit, the central-control unit including a cache memory which temporarily stores some of the information, and a DMA buffer which temporarily stores a DMA address indicated by the direct memory access.
According to one aspect of the present invention, the system as described above is such that the central-control unit invalidates a cache address in the cache memory when the DMA address stored in the DMA buffer matches the cache address.
According to another aspect of the present invention, the system as described above is such that the cache memory includes an instruction-cache memory which stores instructions as part of the information, and an operand-cache memory which stores operands as part of the information, and such that the central-control unit includes a cache-invalidation buffer which temporarily stores an operand-write address when an operand is written in the operand-cache memory, and invalidates a cache address in the cache memory when the operand-write address stored in the cache-invalidation buffer matches the cache address.
According to another aspect of the present invention, a system includes a main-memory unit, an input/output-control unit which performs a write operation with respect to the main-memory unit by way of direct memory access, a CPU which operates based on information stored in the main-memory unit, a cache memory which temporarily stores some of the information, and avails the some of the information to the CPU when the CPU makes a cache request, a DMA buffer which temporarily stores a DMA address indicated in the direct memory access, and a cache-control unit which gives priority to a cache-invalidation request over the cache request from the CPU when the cache-invalidation request is generated in connection with the direct memory access, and accesses the cache memory at the same speed as the CPU accesses the cache memory, so as to invalidate a cache address in the cache memory when the DMA address stored in the DMA buffer matches the cache address.
According to another aspect of the present invention, the system as described above further includes a bus-request-control-and-bus-interface-control unit which generates the cache-invalidation request and stores the DMA address in the DMA buffer upon a bus request when the input/output-control unit issues the bus request in an attempt to perform the write operation with respect to the main-memory unit.
According to another aspect of the present invention, the system as described above is such that the bus-request-control-and-bus-interface-control unit put another bus request on a hold when another input/output-control unit makes the another bus request in an attempt to perform a write operation with respect to the main-memory unit while the DMA buffer indicates a busy status.
According to another aspect of the present invention, the system as described above is such that the cache memory includes an instruction-cache memory which stores instructions as part of the information, and an operand-cache memory which stores operands as part of the information, and such that the cache-control unit includes an instruction-cache-control unit which controls access to the instruction-cache memory, an operand-cache-control unit which controls access to the operand-cache memory, and a cache-invalidation buffer, provided in the operand-cache-control unit, which temporarily stores an operand-write address when an operand is written in the operand-cache memory by a request from the CPU, wherein the instruction-cache-control unit invalidates a cache address in the instruction-cache memory when the operand-write address stored in the cache-invalidation buffer matches the cache address.
According to another aspect of the present invention, the system as described above is such that the instruction-cache-control unit and the operand-cache-control unit operate independently of each other when attending to requests from the CPU as the CPU attempts to access the instruction-cache memory and the operand-cache memory.
In the present invention as described above, the system having the central-control unit, the main-memory unit, and the input/output-control unit connected via a system bus is provided with the cache memory for temporarily storing data in the central-control unit and the DMA buffer for temporarily storing a DMA address when a DMA-write operation is conducted by the input/output-control unit. In this configuration, the DMA address at which the input/output-control unit accesses the main-memory unit is held in the storage, and an address comparison is made between the DMA address in the storage and cache addresses so as to check if there is an address match.
If a match is found between the DMA address stored in the DMA buffer and any cache address of the cache memory, the matched address of the cache memory is invalidated by the central-control unit, so that consistency is maintained between the contents of the cache memory and the contents of the main-memory unit.
Further, the cache memory is divided into the instruction-cache memory and the operand-cache memory, and a buffer is provided to store an operand-write address when a write operation is conducted with respect to the operand-cache memory. The central-control unit invalidates a pertinent address of the instruction-cache memory if this address of the instruction-cache memory matches the operand-write address stored in the buffer.
This configuration allows the instruction and operand cache-control units to operate independently of each other, while insuring data consistency between the instruction-cache memory and the operand-cache memory as well as between the cache memories and the main-memory unit, thereby enhancing the system performance.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.